Fabric.AI, an AI infrastructure company developing a suite of fabless semiconductor technologies for next-generation AI factories, today announces that it has filed a patent application with the United States Patent and Trademark Office (USPTO) titled, "LED Emitter Array Optical Interconnect with Surplus Physical Channels for Data Center Computing." The Company continues to pursue securing its intellectual property jointly owned with its partner Kopin Corporation. Through their partnership, Fabric.AI and Kopin are jointly developing MicroLED-based optical interconnect technology designed to address bandwidth and energy-efficiency constraints in next-generation AI data centers.

The design also spreads error-correction data across the whole array. Because the system knows exactly which channel has failed, it can rebuild the lost information without interrupting traffic. Fabric.AI believes that same margin could also support higher speeds per channel, and its internal modeling points to a path from 2 Gbps toward 2.5 to 3 Gbps. These are projections, not shipping specifications.

"Micro-LED array can be built with surplus channels that are typically held in reserve until something fails," said James Altucher, FabricAI Strategic Advisor and co-author of the patent application. "We see an opportunity to use those spare emitters both to keep a link running through a failure and to carry the small, urgent signals that coordinate a training cluster, such as when each GPU reports that it has finished its step. Today, those signals can queue behind other traffic. Giving them their own optical path is one of the ways we believe Neural I/oTM can help data centers improve utilization and get more computing output from their existing GPUs."

Spare channels, with a clear order of priority
In the architecture described in the patent application, redundancy and repair always come first. If an emitter-detector pair fails, a spare takes its place, and the system can reclaim any spare channel allocated to another use.

The application also describes spreading error-correcting codes across the array. Because the system knows which channel has failed, it can treat the missing data as an error at a known position and correct it without interrupting traffic. Fabric.AI believes this error-correction margin could also allow each LED to run faster, with Company modeling indicating a path from 2 Gbps per channel toward 2.5 to 3 Gbps.

Barrier sync: a faster way to say "I'm done"
During distributed AI training, participating GPUs must finish their assigned work and synchronize at designated points before proceeding. In conventional systems, that "I'm done" signal travels over the same SerDes links as other traffic and can wait in line behind bulk data.

In the proposed architecture, each GPU signals readiness by lighting one or two spare emitters directly onto a shared photodetector, and a comparator detects when the last GPU is ready, greatly increasing GPU utilization.

Additional uses include clock distribution, isolating latency-critical traffic, and analog computation.

The application adds to Fabric.AI's growing intellectual property position around Neural I/o™, the MicroLED-based optical interconnect architecture the Company is developing in collaboration with Kopin to address the data-movement, bandwidth and energy-efficiency demands of next-generation AI infrastructure. The Company continues to expect to demonstrate functioning Neural I/o hardware in January 2027.

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